This sets of mcq's includes onjectives on Application Specific Integrated Circuit in VLSIDT with answers....
SET 1 of Application Specific Integrated Circuit mcq
1. Which Hardware description language is used for ASICs?
a. system verilog
b. system c
c. C++
d. verilog
Answer:-d. verilog
2. What happens when NMOS gate is at a low voltage?
a. P-Type body is at low voltage
b. Source-body and drain-body diodes are off
c. No current flows, transistor is off
d. All of the above
Answer:-d. All of the above
3. What are the different formats that Parasitics are extracted from a layout:
a. DSPF
b. SPEF
c. Both a and b
d. None of the above
Answer:-c. Both a and b
4. Design rules does not specify __________
a.linewidths
b.separations
c.extensions
d.colours
Answer:- d.colours
5. When drain voltage equals the pinch-off-voltage, then drain current …………. with the increase in drain voltage
a. decreases
b. increases
c. remains constant
d. none of the above
Answer:-c. remains constant
6. Delay between shortest path and longest path in the clock is called ____.
a. Useful skew
b. Local skew
c. Global skew
d. Slack
Answer:-c. Global skew
7. Cross talk can be avoided by ___.
a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets
Answer:- b. Shielding the nets
8. Which of the following is having highest priority at final stage (post routed) of the design ___?
a. Setup violation
b. Hold violation
c. Skew
d. None
Answer:- b. Hold violation
9. Hold time is defined as the time required for the data to ________ after the triggering edge of clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above
Answer:- c. Remain stable
10. Which among the following is/are taken into account for post-layout simulation?
a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above
Answer:- d. All of the above
11. Which functions are performed by static timing analysis in simulation?
a. Computation of delay for each timing path
b. Logic analysis in a static manner
c. Both a and b
d. None of the above
Answer:- c. Both a and b
12. In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and b
d. None of the above
Answer:- b. Back end
SET 2 of Application Specific Integrated Circuit mcq
13. The electrical behaviour of a circuit is given using
a) design rules
b) floor plan
c) structures and layouts
d) mathematical modelling
Answer:- d) mathematical modelling
14. Channel length modulation is for voltages
a) exceeding threshold
b) exceeding onset of saturation
c) exceeding power supply
d) exceeding onset of non saturation
Answer:- b) exceeding onset of saturation
15. Circuit design concepts can also be represented using a symbolic diagram.
a) true
b) false
Answer:- a) true
16. Circuit designers need _______ circuits.
a) tighter
b) smaller layout
c) decreased silicon area
d) all of the mentioned
Answer:- d) all of the mentioned
17. Design rules does not specify __________
a) linewidths
b) separations
c) extensions
d) colours
Answer:-d) colours
18. What should be the spacing between two diffusion layers?
a) 4λ
b) λ
c) 3λ
d) 2λ
Answer:- c) 3λ
19. Which design method occupies or uses lesser area?
a) lambda rules
b) micron rules
c) layer rule
d) source rule
Answer:-b) micron rules
20. Which among the following is/are taken into account for post-layout simulation?
a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above
Answer:-d. All of the above
21. Which process deals with the determination of resistance & capacitance of interconnections in VLSI design?
A. Testing
B. Extraction
C. Floorplanning
D. Placement & Routing
Answer:-B. Extraction
22. The Solution for Antenna effect is ___.
a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing
Answer:-a. Diode insertion
23. Cross talk can be avoided by ___.
a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets
Answer:-
24. Which functions are performed by static timing analysis in simulation?
a. Computation of delay for each timing path
b. Logic analysis in a static manner
c. Both a and b
d. None of the above
Answer:-c. Both a and b
25. Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________ path delay between consecutive flip-flops.
a. shortest
b. average
c. longest
d. unpredictable
Answer:-b. average
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