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Digital design and Issues MCQ with answers in VLSIDT - Part 2





This sets of mcq most on digital design and issues, Moore and Mealy machines, Clock jitter, Supply and ground bounce in vlsidt...

SET 1 of Digital design and Issues MCQ

1. Which factors affects the signal integrity of an instrument? 
a) Bends
b) Crosstalk
c) Stub length
d) All of the above

Answer:-d) All of the above 

2. Timing performance of a design is measure by which simulation mode?
a. Behavioural
b. Gate-level
c. Switch-level
d. Transistor-level

Answer:-b. Gate-level 

3. In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities?
a. Power/Ground Noise
b. Crosstalk Noise
c. Reflection Noise
d. All of the above

Answer:-c. Reflection Noise 

4. _______path for a single wire between a set of points is determine by Maze routing.
a. Shortest
b. Average
c. Longest
d. None of the above

Answer:-a. Shortest 

5. Which are easier to design?
a. clocked circuits
b. asynchronous sequential circuits
c. clocked circuits with buffer
d. asynchronous sequential circuits with buffers

Answer:-a. clocked circuits 

6. Why Clock distribution require in digital systems?
a. to reduce delay
b. to increase speed 
c. to keep operations in sequence
d. to reduce area

Answer:-c. to keep operations in sequence 

7. It is a phenomenon in synchronous circuits in which the clock signal arrives at different components at different times.
a. jitter
b. skew
c. pulse
d. All of the above

Answer:-b. skew

8. The main job of the clock routing design is to control
a. skew
b. jitter
c. latency
d. all of the above

Answer:-a. skew 

9. Clocking is a
a. floor planning problem
b. placement problem
c. mapping problem
d. all of the above

Answer:-a. floor planning problem 

10. deviation of a clock edge from its ideal position
a. jitter
b. skew
c. latency
d. all of the above

Answer:-a. jitter

SET 2 Digital design and Issues MCQ

11. what is ground bounce?
a. In a system, the tiny wire connection between the chip and the lead frame of the package contributes a small amount of inductance in the circuit.
b. When Vout goes low, a spike of current flows through this inductance and creates a voltage spike.
c. When Vout goes high, a spike of current flows through this inductance and creates a voltage spike.
d. a and b
e. a and c

Answer:-d. a and b 

12. If power dissipation and propagation delay in a logic circuit are estimated to be 55mW and 25ns respectively, what will be its figure of merit?
a. 1.20 nanojoule
b. 1.25 nanojoule
c. 1.10 nanojoule
d. 1.37 nanojoule

Answer:-d. 1.37 nanojoule 

13. What should be the value of input voltage for an efficient operation of a digital circuit by avoiding the conditions of invalid voltage levels?
a. Lower than VIL (max)
b. Higher than VIH (min)
c. Both a and b
d. None of the above

Answer:-c. Both a and b 

14. From where do the voltage noise get induced into to digital circuit?
a. From a gate output to load
b. From the connecting wires used between two gates
c. Both a and b
d. None of the above

Answer:-c. Both a and b 

15. Which steps measures the resistance & capacitance of interconnections in VLSI design flow?
a. Testing
b. Extraction
c. Floorplanning
d. Placement & Routing

Answer:-b. Extraction 

16. What is common in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above 

Answer:-b. Clocked Process 


17. Switching power dissipation can be given as
a. Cl x Vdd x f
b. Vdd2 x f
c. Cl x Vdd2 x f
d. Cl x Vdd2 

Answer:-c. Cl x Vdd2 x f 

18. In CMOS domino logic------------- is used
a) one phase clock
b) two phase clock
c) three phase clock
d) four phase clock

Answer:-a) one phase clock 

19. Which among the following operation/s is/are executed in physical design or layout synthesis stage?
a. Placement of logic functions in optimized circuit in target chip
b. Interconnection of components in the chip
c. Both a and b
d. None of the above

Answer:-c. Both a and b





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