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Microcontroller MCQ's Questions With Answers For Exams 5





Some Microcontroller important MCQ's questions for university exams, Placements, companies exams, GATE and other exams preparations with answers.

1) Which abstraction level undergo the compilation process by converting a sequential program
into finite-state machine and register transfers while designing an embedded system?

a. System
b. Behaviour
c. RT
d. Logic

ANSWER: Behaviour

2) What are the essential tight constraint/s related to the design metrics of an embedded system?


a. Ability to fit on a single chip
b. Low power consumption
c. Fast data processing for real-time operations
d. All of the above

ANSWER: All of the above

3) Which feature deals with the fetching of next instruction during the execution of current
instruction irrespective of the memory access?

a. Fetching 
b. Pre-fetching
c. Fetch & Decoding
d. All of the above

ANSWER: Pre-fetching

4) Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for
program and data fetching purposes?

a. Time Division Multiplexing
b. Frequency Division Multiplexing
c. Statistical Time Division Multiplexing
d. Code Division Multiplexing

ANSWER: Time Division Multiplexing

5) Which factors/parameters contribute to an effective utilization or adoption of Harvard
architecture by most of the DSPs for streaming data?

a. Greater memory bandwidth
b. Predictable nature of bandwidth
c. Both a & b
d. None of the above 

ANSWER: Both a & b

6) Which architectural scheme has a provision of two sets for address & data buses between CPU
and memory?

a. Harvard architecture
b. Von-Neumann architecture
c. Princeton architecture
d. All of the above

ANSWER: Harvard architecture

7) Which register of current procedure resemble physically similar to the parameter register of
called procedure during register to register operation in an overlapping window of RISC Processors?

a. Local Register
b. Temporary Register
c. Parameter Register
d. All of the above

ANSWER: Temporary Register

8) What does the compact and uniform nature of instructions in RISC processors facilitate to?

a. Compiler optimization
b. Pipelining
c. Large memory footprints
d. None of the above

ANSWER: Pipelining

9) What are the significant designing issues/factors taken into consideration for RISC Processors?

a. Simplicity in Instruction Set
b. Pipeline Instruction Optimization
c. Register Usage Optimization
d. All of the above

ANSWER: All of the above

10) How are the address and data buses removed in external memory type of microcontrollers?

a. Through demultiplexing by external latch & ALE signal 
b. Through demultiplexing by external latch & DLE signal
c. Through multiplexing by external latch & DLE signal
d. Through multiplexing by external latch & ALE signal

ANSWER: Through multiplexing by external latch & ALE signal

11) External Memory Microcontrollers can overcome the limitations of insufficient in-built program
and data memory by allowing the connections of external memory using _________

a. Serial Port Pins as address and data lines
b. Parallel Port Pins as address and data lines
c. Parallel Port Pins as address and control lines
d. Serial Port Pins as address and control lines

ANSWER: Parallel Port Pins as address and data lines

12) Which category of microcontrollers acquire the complete hardware configuration on its chip so
as to run the particular application?

a. Embedded Memory Microcontrollers
b. External Memory Microcontrollers
c. Both a & b
d. None of the above

ANSWER: Embedded Memory Microcontrollers

13) Which microcontrollers offer the provisional and salient software features of fault handling
capability, interrupt vector efficiency and versatile addressing?

a. TMS 1000 (4 bit)
b. TMS 7500 (8 bit)
c. Intel 8096 (16 bit)
d. Intel 80960 (32 bit)

ANSWER: Intel 80960 (32 bit)

14) Which among the below stated statements does not exhibit the characteristic feature of 16-bit
microcontroller?

a. Large program & data memory spaces
b. High speed
c. I/O Flexibility
d. Limited Control Applications

ANSWER: Limited Control Applications

15) Which word size is approved to be of greater importance for performing the small computational
tasks along with its storage usability feature adopted by ASCII code?

a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit

ANSWER: 8-bit

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16) Which minimum mode signal is used for demultiplexing the data and address lines with the
assistance of an external latch in a microprocessor while accessing memory segment?

a. INTA
b. DTE
c. HOLD
d. ALE

ANSWER: ALE

17) Why do the microprocessors possess very few bit manipulating instructions?

a. Because they mostly operate on bits/ word data
b. Because they mostly operate on byte/word data
c. Both a & b
d. None of the above 

ANSWER: Because they mostly operate on byte/word data

18) How does the microcontroller communicate with the external peripherals/memory?

a. via I/O ports
b. via register arrays
c. via memory
d. All of the above

ANSWER: via I/O ports

19) Which functioning element of microcontroller generate and transmit the address of instructions
to memory through internal bus?

a. Instruction Decoding Unit
b. Timing and Control Unit
c. Program Counter
d. Arithmetic Logic Unit

ANSWER: Program Counter

20) Which instructions contribute to an effective adoption or utilization of stack memory which
usually plays a crucial role in storage of intermediate results?

a. ACALL
b. RETI
c. PUSH & POP
d. All of the above

ANSWER: All of the above

21) What does the following pictorial representation of PUSH operation in the stack pointer indicate
among the below stated conclusions/inferences?
a. Stack Pointer is incremented by 2
b. Location 55H in on-chip stack memory gets loaded with 44H
c. Stack Pointer gets initialized by 56H
d. Data Pointer gets loaded with an immediate data 44H which ultimately leads to initialization of stack
pointer

a. Only A
b. Only B
c. B & D
d. C & D

ANSWER: C & D

22) What is the status of stack pointer for the execution of PUSH and POP operations?

a. It gets post-decremented for PUSH & pre-incremented for POP
b. It gets pre-incremented for PUSH & post-decremented for POP
c. It gets pre-incremented for PUSH as well as POP
d. It gets post-decremented for PUSH as well as POP

ANSWER: It gets pre-incremented for PUSH & post-decremented for POP

23) What is the correct chronological order of the following steps involved in the LCALL operation?
1. Load the value of 16-bit destination address to program counter
2. Increment of the program counter by value '3'
3. Storage of the higher byte of program counter on the stack
4. Increment of the stack pointer by value'1'
5. Storage of the lower byte of program counter on the stack
6. Increment in the value of stack pointer

a. 5, 3, 1, 6, 2, 4
b. 1, 3, 2, 5, 4, 6
c. 2, 4, 5, 6, 3, 1
d. 5, 3, 6, 2, 4, 1

ANSWER: 2, 4, 5, 6, 3, 1

24) Match the following instruction mnemonics with their description.
a. CJNE A,direct,rel ------------ 1. Compare immediate to indirect and Jump if not equal
b. CJNE A,#data,rel ------------ 2. Compare direct byte to accumulator and Jump if not equal
c. CJNE @Ri, #data,rel ------- 3. Compare immediate to register and Jump if not equal
d. CJNE Rn, # data rel -------- 4. Compare immediate to accumulator and Jump if not equal

a. A-1, B-2, C-3, D-4
b. A-2, B-4, C-1, D-3
c. A-4, B-3, C-2, D-1
d. A-2, B-4, C-3, D-1

ANSWER: A-2, B-4, C-1, D-3

25) Consider the below mentioned statements. Which among them is /are approved to be incorrect
in case of calling instructions of program branching?
a. Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program
memory block 
b. Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory
block
c. Short call instructions specify 16-bit address and subroutine within 4K program memory block
d. All long call and short call instructions specify 11 bit address and the calling subroutine within 16K
program memory block

a. Only A
b. B & D
c. A & C
d. C & D

ANSWER: C & D

26) Which among the category of program branching instructions allow 16 bit address to be
specified & can jump anywhere within 64K block of program memory?

a. Long jumps (LJMP)
b. Short jumps (SJMP)
c. Absolute jumps (AJMP)
d. All of the above

ANSWER: Long jumps (LJMP)

27) What is the possible range of transfer control for 8-bit relative address especially in 2's
complement form with respect to the first byte of preceding instruction? 

a. -115 to 132 bytes
b. -130 to 132 bytes
c. -128 to 127 bytes
d. -115 to 127 bytes


ANSWER: -128 to 127 bytes

28) Match the following
a. JC rel -------------------- 1. Jump if direct bit is set & clear bit
b. JNC rel ------------------ 2. Jump if direct bit is set
c. JB bit, rel --------------- 3. Jump if direct bit is not set
d. JBC bit, rel ------------ 4. Jump if carry is set
e. JNB bit, rel ------------- 5. Jump if carry is not set

a. A-3, B-2, C-1, D-4, E-5
b. A-5, B-2, C-4, D-1, E-3
c. A-5, B-4, C-3, D-2, E-1
d. A-4, B-5, C-2, D-1, E-3


ANSWER: A-4, B-5, C-2, D-1, E-3

29) Which among the single operand instructions complement the accumulator without affecting
any of the flags? 
a. CLR
b. SETB
c. CPL
d. All of the above

ANSWER: CPL

30) Which rotate instruction/s has an ability to modify CY flag by moving the bit-7 & bit-0
respectively to an accumulator?

a. RR & RL
b. RLC & RRC
c. RR & RRC
d. RL & RLC

ANSWER: RLC & RRC

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