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PLD Architectures and applications MCQ with answers - Part 1





This sets of mcq most includes questions on PLD architecture and its applications, Features, Specifications, FPGA Architecture, Features, Specifications, Applications...

SET 1 of PLD Architectures and applications MCQ

1. What programmable technology is used in FPGA devices?
a) SRAM
b) FLASH
c) ANTIFUSE
d) All of the above

Answer:-d) All of the above

2. What does a dot mean when placed on a PLD circuit diagram?
a) an input or output point
b) a programmable point
c) a point that cannot change
d) None of the above

Answer:-c) a point that cannot change

3. AND Array is programmable in __________
a) PLA
b) PROM
c) PAL
d) a &c

Answer:-d) a &c

4. Which is the main programming unit in FPGA?
a) Programmable AND Array
b) Configurable Logic Block
c) Programmable OR Array
d) None of the above 

Answer:-b) Configurable Logic Block

5. _________________ is having programmable AND array and fixed OR array
a) PLA
b) FPGA
c) PAL
d) All of the above

Answer:-c) PAL

6) In which of the following PLD’s both AND and OR array are programmable?
a) PAL
b) PLA
c) ASIC
d) FPGA

Answer:-b) PLA

7) A CPLD 36V18 has:
a) 18 inputs and 36 outputs
b) 36inputs and 18 outputs
c) Both a and b
d) None of the above

Answer:-b) 36inputs and 18 outputs

8) Which are the components of the CPLD architecture?
a) Switch Matrix
b) Functional Blocks
c) I/O Blocks
d) All of the above

Answer:-d) All of the above

9) A functional block in CPLD consists of _______.
a) Programmable AND array
b) Microcells
c)Product Term Allocators
d) All of the above 

Answer:-d) All of the above

10) Configurable logic blocks in FPGA are based on
a) Look up tables
b) Programmable Interconnect
c) Carry look ahead logic
d) None of the above

Answer:-a) Look up tables

SET 2 of PLD Architectures and applications MCQ

11) What does a cross mean when placed on a PLD circuit diagram?
a) an input or output point
b) a programmable point
c) a point that cannot change
d) None of the above

Answer:-b) a programmable point

12. A ________ is a simple one bit memory element.
a) FB
b) CLB
c) LUT
d) All of the mentioned

Answer:-c) LUT 

13) In FPGA, _______________ provides interface between package pins and CLBs
a) Input Output Blocks
b) Functional Blocks
c) Both a and b
d) None of the a and b

Answer:-a) Input Output Blocks

14) Post Layout Simulations include _________
a) Set up and hold times
b) Component and wire delays
c) Clock Skew
d) All of the above 

Answer:-d) All of the above 

15. A ___________ converts HDL code into a gate level netlist.
a. Compiler
b. Simulator
c. Synthesizer
d. All of the above

Answer:-c. Synthesizer

16. For high performance and low power application which is preferred?
a. Application Specific Integrated Circuits
b. Field Programmable Gate Arrays
c. Complex Programmable Logic Devices
d. None of the above

Answer:-a. Application Specific Integrated Circuits

17. The features of the XC9500 CPLD family are
a) High Performance
b) In system programmability
c) Flexible 36V18 Function Block
d) All of the above

Answer:-d) All of the above

18. Which one of the following are Programmable Logic Devices?
a) SPLD
b) CPLD
c) FPGA
d) All of the above

Answer:-d) All of the above

19. Which of the following belongs to the SPLD category?
a) PAL
b) CPLD
c) GAL
d) Both a and c 

Answer:-d) Both a and c 

20. Vertical and horizontal directions in FPGA are separated by_______
a. A channel
b. A Line
c. A Flip Flop
d. A strobe 

Answer:-a. A channel
 





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